28F016XS 查看數據表（PDF） - Intel

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28F016XS

16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY

Intel 

28F016XS FLASH MEMORY

E

4.3 28F008SA—Compatible Mode Command Bus Definitions

Command

Read Array

Intelligent Identifier

Read Compatible Status Register

Clear Status Register

Program

Alternate Program

Block Erase/Confirm

Erase Suspend/Resume

Notes

1

2

3

First Bus Cycle

Oper Addr Data(4)

Write

X

xxFFH

Write

X

xx90H

Write

X

xx70H

Write

X

xx50H

Write

X

xx40H

Write

X

xx10H

Write

X

xx20H

Write

X

xxB0H

Second Bus Cycle

Oper Addr Data(4)

Read

AA

AD

Read

IA

ID

Read

X

CSRD

Write

Write

Write

Write

PA

PD

PA

PD

BA xxD0H

X

xxD0H

ADDRESS

AA = Array Address

BA = Block Address

IA = Identifier Address

PA = Program Address

X = Don’t Care

DATA

AD = Array Data

CSRD = CSR Data

ID = Identifier Data

PD = Program Data

NOTES:

1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register

definitions.

4. The upper byte of the data bus (D8–15) during command writes is a “Don’t Care” in x16 operation of the device.

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