TQ8101-M 查看數據表（PDF） - TriQuint Semiconductor
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TQ8101-M Datasheet PDF : 14 Pages
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TQ8101C
SONET/SDH Considerations
Jitter Tolerance
This measurement does not apply to the TQ8101C,
since data is transmitted from the input parallel bus
relative to a TQ8101C-generated clock output
(MXCK[2:0]). The user must meet setup and hold time
requirements in order to ensure that data tracking is
maintained.
Jitter Generation
By exploiting material characteristics, fully differential
SCFL logic, and on-chip reactive elements, the
TQ8101C typically has a jitter generation of 0.008 UI
RMS (where 1 UI is 1/622.08E06) using recommended
loop filter component values.
Ordering Information
TQ8101-M
SONET/SDH MDFP
Evaluation Board Please contact a TriQuint representative or the factory
for availability and pricing.
Additional Information
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com Tel: (503) 615-9000
Email: sales@tqs.com Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.1.A November 1997
14
For additional information and latest specifications, see our website: www.triquint.com
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