TRC101 查看數據表（PDF） - RF Monolithics, Inc

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TRC101

300-1000 MHz RF Transceiver

RF Monolithics, Inc 

Receiver Control Register [POR=9080h]

Bit Bit Bit Bit Bit Bit

Bit

Bit Bit Bit Bit Bit

Bit

Bit

Bit

Bit

15 14 13 12 11 10

9

8

765

4

3

2

1

0

1 0 0 1 0 INT/VDI VDIR1 VDIR0 BB2 BB1 BB0 GAIN1 GAIN0 RSSI2 RSSI1 RSSI0

The Receiver Control Register configures the following:

• Receiver LNA gain

• Digital RSSI threshold

• Receive baseband bandwidth

• Valid Data Detector response time

• Function of pin 16

Bit [15..11] – Command Code: These bits are the command code that is sent serially to the processor

that identifies the bits to be written to the Receiver Control Register.

Bit [10] – Pin 16 Func: Selects the function of Pin 16. See Table 10 below.

Table 10.

Pin 16 Function INT/VDI

Interrupt Input

0

Valid Data Output 1

Bit [9..8] – Valid Data Detector Response Time: When Pin 16 is selected as Valid Data Detector output

these bits set the response time in which the TRC101 will detect the incoming synchronous bit pattern

and issue an interrupt to the host processor. See Table 11 below for response settings.

Table 11.

VDI Response Time VDIR1

Fast

0

Mid

0

Slow

1

Continuous

1

VDIR0

0

1

0

1

Figure 4. VDI Signal Response Configuration

19

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