UPD6124A 查看數據表（PDF） - NEC => Renesas Technology
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UPD6124A Datasheet PDF : 36 Pages
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µPD6124A, 6600A
11.5 S-OUT PIN
By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that communication
is in progress.
The S-OUT pin is CMOS output.
The S-OUT pin goes high on reset.
11.6 S-IN PIN (D0 BIT OF P1)
To input serial data, use the S-IN pin. When control register (P1) is set to serial input mode, the S-IN pin is connected
as an input to the LSB of the accumulator; the S-IN pin can be pulled down to the VSS level by a mask option from within
the LSI. In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is copied
to the LSB of the accumulator.
If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no through
current flows internally.
When the RL A instruction is executed, the MSB is copied to the LSB.
At reset (all cleared), the S-IN pin goes into a high-impedance state.
Caution The µPD6123 is not provided with an S-IN pin.
Figure 11-3. Configuration of the S-IN Pin
CY
A3
A2
A1
A0
S-IN
Control register
11
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