VSC9110SA 查看數據表（PDF） - Vitesse Semiconductor

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VSC9110SA

STS-48 Physical Layer ATM UNI/NNI Device

Vitesse Semiconductor 

STS-48 Physical Layer

ATM UNI/NNI Device

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC9110

Figure 2: Tx Line Interface Timing Dependencies

TLCLK+

TLOUT[15..0]+/-

TLPRTY+/-

TLFP+/-

TLCLKOUT+

TP,TLOUT

TP,TLCLKOUT

TXRCLK

TP,TXRCLK

TSU,TLIN

TH,TLIN

TLSYNC+/-

TPW, TLSYNC

Table 2: Tx Line Interface

Symbol

Description

Min Max

fTLCLK

dcTLCLK

TR/F, TLCLK

TP, TLOUT

TLCLK+/- Clock Frequency (nominal)

TLCLK+/- Duty Cycle

TLCLK+/- Rise/Fall Time

TLCLK+ Rising Edge to TLOUT[15..0]+/- and TLPRTY+/-,

TLFP+/- Valid

-

155.52

40

60

-

1.0

1.0

4.0

TP, TXRCLK

TP, CLKOUT

TLCLK+ Rising Edge to TXRCLK Rising/Falling Edge

1.0

20.0

TLCLKOUT+ Rising Edge to TLOUT[15..0]+/-, TLPRTY+/-,

TLFP+/- Valid

0

1.3

fTXRCLK

fTLCLK Divided by 2/4/8/19440

-

-

dcTXRCLK

TSU, TLIN

TH, TLIN

TXRCLK Duty Cycle

TLSYNC +/- Setup Time to TLCLK+ Rising Edge 1)

TLSYNC +/- Hold Time to TLCLK+ Rising Edge 1)

30

70

2.0

1.0

TPW, TLSYNC

Minimum Pulse Width of TLSYNC (measured in TLCLK Clock

Cycles)

2

1) It is not required that TSU, TLIN and TH, TLIN are met.

TXRCLK times are for 50 pF load.

TLOUT[15..0], TLFP, TLPRTY and TLCLKOUT are for 0.5 pF load. Add 0.3 ns for each pF of extra load.

Unit

MHz

%

ns

ns

ns

ns

MHz

%

ns

ns

-

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52198-0, Rev. 4.2

1/8/00

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