28C256 查看數據表（PDF） - Xicor -> Intersil

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28C256

32K x 8 Bit 5 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

X28C256

DATA Polling Timing Diagram(12)

ADDRESS

An

An

An

CE

WE

tOEH

OE

I/O7

DIN=X

Toggle Bit Timing Diagram(12)

CE

DOUT=X

tWC

tOES

tDW

DOUT=X

3855 FHD F09

WE

tOEH

OE

I/O6

HIGH Z

*

*

tWC

* Starting and ending state of I/O6 will vary, depending upon actual tWC.

Note: (12) Polling operations are by definition read cycles and are therefore subject to read cycle timings.

tOES

tDW

3855 FHD F10

15

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