Z53C80 查看數據表（PDF） - Zilog
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Z53C80 Datasheet PDF : 40 Pages
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ZILOG
AC CHARACTERISTICS
DMA Write Initiator Send Cycle Table
No
Description
1
DRQ Low from /DACK Low
2
/DACK High to DRQ High
3
Write Enable Width [1]
4
/DACK Hold from End of /WR
5
Data Setup to End of Write Enable [1]
6
Data Hold Time from End of /WR
7
Width of /EOP Pulse [2]
8
/REQ Low to /ACK Low
9
/REQ High to DRQ High
10
/DACK High to /ACK High
11
/WR High to Valid SCSI Data
12
Data Hold from Write Enable [1]
13
Data Setup to /ACK Low
Notes:
[1] Write Enable is the occurrence of /WR and /DACK.
[2] /EOP, /WR, and /DACK must be concurrently Low for at least T7 for
proper recognition of the /EOP pulse.
Z53C80 SCSI
Min
Max
60
30
50
0
50
25
50
90
70
90
50
15
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PS97SCC0200
27
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