CYS25G0101DX-AEXC 查看數據表（PDF） - Cypress Semiconductor

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CYS25G0101DX-AEXC

SONET OC-48 Transceiver

Cypress Semiconductor 

CYS25G0101DX

Clocking

The source clock for the transmit data path is selectable from

either the recovered clock or an external BITS (Building

Integrated Timing Source) reference clock. The low jitter of the

CDR PLL enables loop timed operation of the transmit data path

meeting all Bellcore and ITU jitter requirements.

Multiple loopback and loop through modes are available for both

diagnostic and normal operation. For systems containing

redundant SONET rings that are maintained in standby, the

CYS25G0101DX may also be dynamically powered down to

conserve system power.

Figure 1. CYS25G0101DX System Connections

SONET Data

CYS25G0101DX

16

Processor

TXD[15:0]

TXCLKI

Transmit Data

Interface

FIFO_RST

FIFO_ERR

TXCLKO

REFCLK

2

155.52 MHz

BITS Time

Host Bus

Receive Data

16

RXD[15:0]

Reference

Interface

Interface

RXCLK

Data & Clock

Direction

Control

LOOPTIME

DIAGLOOP

LOOPA

LINELOOP

IN+

IN–

SD

OUT–

OUT+

Serial Data

Serial Data

RD+

RD–

SD

TD–

Optical

XCVR

TD+

Status and

System

Control

RESET

PWRDN

LOCKREF

LFI

Optical

Fiber Links

Document Number: 38-02009 Rev. *O

Page 4 of 22

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