AS3588AQ 查看數據表（PDF） - austriamicrosystems AG
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AS3588AQ Datasheet PDF : 15 Pages
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Data Sheet
AS3588A
Write Timing Characteristics (Figure 6): Operation over recommended temperature and voltage range
Symbol Parameter
Condition
Min.
Typ.*
Max. Units
tWLWR Write Pulse Low Width
150
ns
tWHWR Write Pulse High Width
tCK
ns
tREP
Repetition Interval be-
tREP=40+2 tCK+tWLCK
see
ns
tween active Write Pulses + tRCK
formula
tSHRD
High Level Setup Time to
0
ns
active Read Pulse
tHHRD
High Level Hold Time from
20
ns
active Read Pulse
tRWR
Write Pulse Rise Time
60
ns
tFWR
Write Pulse Fall Time
tSLCSWR CS Low Setup Time to
WR Falling Edge
Active State
0
tHLCSWR CS Low Hold time from
WR Rising Edge
Active State
0
tSHCSWR CS High Setup Time to
WR Falling Edge
Inative State
0
tHHCSWR CS High Hold Time from
WR Rising Edge
Inactive State
0
tSCDWR C/D Setup Time to Write
Pulse End
130
tHCDWR C/D Hold Time from Write
Pulse End
25
tSASWR Address Select Setup Time
to Write Pulse End
130
tHASWR Adress Select Hold Time
from Write Pulse End
25
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWDR
Data Ready Low Time
Opcodes 5, 6
2 tCK
ns
tPDDR
Data Ready Delay Time Opcode 5; CL=50pF
from Write Pulse End
Active Opcode
5 tCK
14 tCK
tSDWR
Data Setup Time to Write
PulseEnd
130
ns
tHDWR Data Hold Time from Write
Pulse End
25
ns
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing
Note: Because of internal clock re-synchronization one single additional requirement is recommended in order to produce a
simultaneous instruction execution in a multi-chip configuration: WR rising edge has to be 20 to 20 + tWL(cK) nsec late relative
to clock falling edge.
Rev. 3.1
Page 12 of 15
July 1999
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