CY7C056V-20AI 查看數據表（PDF） - Cypress Semiconductor

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CY7C056V-20AI

3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM

Cypress Semiconductor 

PRELIMINARY

Switching Waveforms (continued)

Interrupt Timing Diagrams

Left Side Sets INTR :

ADDRESS

L

CE0L, CE1L

R/W

L

tWC

WRITE 3FFF (7FFF for CY7C057V)

tHA[42]

CHIP SELECT VALID

INT R

Right Side Clears INTR :

ADDRESSR

tINS [43]

CE0R, CE1R

R/WR

CHIP SELECT VALID

tINR [43]

OE R

INTR

Right Side Sets INTL:

ADDRESSR

CE0R, CE1R

R/W R

INT L

Left Side Clears INT L:

ADDRESSL

tWC

WRITE 3FFE (7FFE for CY7C057V)

tHA[42]

CHIP SELECT VALID

tINS[43]

CE0L,CE1L

R/W L

CHIP SELECT VALID

tINR[43]

OE L

INT L

Notes:

42. tHA depends on which enable pin (CE0L/CE1L or R/WL) is deasserted first.

43. tINS or tINR depends on which enable pin (CE0L/CE1L or R/WL) is asserted last.

tRC

READ 3FFF

(7FFF for CY7C057V)

tRC

READ 3FFE

(7FFF for CY7C057V)

CY7C056V

CY7C057V

15

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