F81865F 查看數據表（PDF） - Feature Integration Technology Inc.
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F81865F Datasheet PDF : 128 Pages
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F81865
Digital Input Register (PC-AT Mode) ⎯ Base + 7
Bit
Name
R/W Default
Description
7
DSKCHG
R
- This bit indicates the complement of DSKCHG# disk interface input.
6-0
Reserved
R
- Reserved.
Digital Input Register (PS/2 Mode) ⎯ Base + 7
Bit
Name
R/W Default
Description
7
DSKCHG
R
- This bit indicates the complement of DSKCHG# disk interface input.
6-3
Reserved
-
- Reserved.
2-1
DRATE
R
10 These bits indicate the status of the DRATE programmed through the Data
Rate Select Register or Configuration Control Register.
0: 1Mbps or 500Kbps data rate is chosen.
0
HIGHDEN_N
R
1
1: 300Kbps or 250Kbps data rate is chosen.
Digital Input Register (Model 30 Mode) ⎯ Base + 7
Bit
Name
R/W Default
Description
7
DSKCHG_N
R
- This bit indicates the state of DSKCHG# disk interface input.
6-4
Reserved
-
- Reserved.
3
DMAEN
R
0 This bit reflects the DMA bit in Digital Output Register.
2
NOPRE
R
0 This bit reflects the NOPRE bit in Configuration Control Register.
1-0
DRATE
These bits indicate the status of DRATE programmed through the Data Rate
R 10
Select Register or Configuration Control Register.
Configuration Control Register (PC-AT and PS/2 Mode) ⎯ Base + 7
Bit
Name
R/W Default
Description
7-2
Reserved
-
- Reserved.
1-0
DRATE
W
10 These bit determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
Configuration Control Register (Model 30 Mode) ⎯ Base + 7
Bit
Name
R/W Default
Description
7-3
Reserved
-
- Reserved.
This bit could be programmed through Configuration Control Register and be
2
NOPRE
W
0 read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no
functionality.
1-0
DRATE
W
10
These bits determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
26
May, 2010
V0.28P
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