GS8170DW36AGC-250 查看數據表（PDF） - Giga Semiconductor

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GS8170DW36AGC-250

18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM™

Giga Semiconductor 

GS8170DW36/72AC-350/333/300/250

Timing Parameter Key—Double Late Write Mode Control and Data In Timing

CK

tAVKH

tKHAX

A

A

B

C

E1, E2, E3,

W, Bx, ADV

tnVKH

tKHnX

DQ (Data In)

tDVKH

DA

tKHDX

Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output

drivers are powered by VDDQ.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

Rev: 1.04 4/2005

21/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2003, GSI Technology

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