HMC5883L 查看數據表（PDF） - Honeywell International
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HMC5883L Datasheet PDF : 18 Pages
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HMC5883L
Identification Register A
The identification register A is used to identify the device. IRA0 through IRA7 indicate bit locations, with IRA denoting the
bits that are in the identification register A. IRA7 denotes the first bit of the data stream. The number in parenthesis
indicates the default value of that bit.
The identification value for this device is stored in this register. This is a read-only register.
Register values. ASCII value H
IRA7 IRA6
IRA5
IRA4
IRA3
IRA2
IRA1
0
1
0
0
1
0
0
Table 18: Identification Register A Default Values
IRA0
0
Identification Register B
The identification register B is used to identify the device. IRB0 through IRB7 indicate bit locations, with IRB denoting the
bits that are in the identification register A. IRB7 denotes the first bit of the data stream.
Register values. ASCII value 4
IRB7
0
IRB6
IRB5
IRB4
IRB3
IRB2
IRB1
0
1
1
0
1
0
Table 19: Identification Register B Default Values
IRB0
0
Identification Register C
The identification register C is used to identify the device. IRC0 through IRC7 indicate bit locations, with IRC denoting the
bits that are in the identification register A. IRC7 denotes the first bit of the data stream.
Register values. ASCII value 3
IRC7 IRC6 IRC5
IRC4
IRC3
IRC2
IRC1
0
0
1
1
0
0
1
Table 20: Identification Register C Default Values
IRC0
1
I2C COMMUNICATION PROTOCOL
The HMC5883L communicates via a two-wire I2C bus system as a slave device. The HMC5883L uses a simple protocol
with the interface protocol defined by the I2C bus specification, and by this document. The data rate is at the standard-
mode 100kbps or 400kbps rates as defined in the I2C Bus Specifications. The bus bit format is an 8-bit Data/Address
send and a 1-bit acknowledge bit. The format of the data bytes (payload) shall be case sensitive ASCII characters or
binary data to the HMC5883L slave, and binary data returned. Negative binary values will be in two’s complement form.
The default (factory) HMC5883L 8-bit slave address is 0x3C for write operations, or 0x3D for read operations.
The HMC5883L Serial Clock (SCL) and Serial Data (SDA) lines require resistive pull-ups (Rp) between the master device
(usually a host microprocessor) and the HMC5883L. Pull-up resistance values of about 2.2K to 10K ohms are
recommended with a nominal VDDIO voltage. Other resistor values may be used as defined in the I2C Bus Specifications
that can be tied to VDDIO.
The SCL and SDA lines in this bus specification may be connected to multiple devices. The bus can be a single master to
multiple slaves, or it can be a multiple master configuration. All data transfers are initiated by the master device, which is
responsible for generating the clock signal, and the data transfers are 8 bit long. All devices are addressed by I2C’s
16
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