INDT165B 查看數據表（PDF） - Unspecified
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INDT165B Datasheet PDF : 41 Pages
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(b) Receiver pixel interface
Data Sheet
INDT/R165B
INDT/R330B
PCLK+
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t5/6
t7
Figure 3.6: Pixel Interface Timing Diagram At Rising Edge At Rx
Parameter
t5
t6
t7
Description
Pixel data and ctrl signal setup time to pixel clock at Rx (SXGA)
Pixel data and ctrl signal setup time to pixel clock at Rx (UXGA)
Pixel data and ctrl signal hold time to pixel clock at Rx
Min.
Typ.
1.8
4.0
1.6
3.0
0.5
1.2
Table 3.12: Pixel Interface Timing Table At Rising Edge At Rx
Max.
4.4
4.2
1.4
Unit
ns
ns
ns
PCLK+
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t8/9
t10
Figure 3.7: Pixel Interface Timing Diagram At Falling Edge At Rx
Parameter
t8
t9
t10
Description
Pixel data and ctrl signal setup time to pixel clock at Rx (SXGA)
Pixel data and ctrl signal setup time to pixel clock at Rx (UXGA)
Pixel data and ctrl signal hold time to pixel clock at Rx
Min.
Typ.
2.2
3.8
1.0
2.9
0.5
1.2
Table 3.13: Pixel Interface Timing Table At Falling Edge At Rx
Max. Unit
4.7
ns
3.7
ns
1.3
ns
Date: 2005-02-18 Revision: 1.1
Page 21 of 41
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