K9G4G08B0A 查看數據表（PDF） - Samsung
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K9G4G08B0A Datasheet PDF : 44 Pages
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K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Preliminary
FLASH MEMORY
Figure 1-1. K9G4G08X0A Functional Block Diagram
VCC
VSS
A12 - A29
X-Buffers
Latches
& Decoders
4,096M + 128M Bit
NAND Flash
ARRAY
A0 - A11
Y-Buffers
Latches
& Decoders
(2,048 + 64)Byte x 262,144
Data Register & S/A
Command
Command
Register
Y-Gating
I/O Buffers & Latches
CE
Control Logic
RE
& High Voltage
WE
Generator
Global Buffers
Output
Driver
CLE ALE WP
VCC
VSS
I/0 0
I/0 7
Figure 2-1. K9G4G08X0A Array Organization
1 Block = 128 Pages
(256K + 8K) Byte
256K Pages
(=2,048 Blocks)
2K Bytes
64 Bytes
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 128 Pages
= (256K + 8K) Bytes
1 Device = (2K+64)B x 128Pages x 2,048 Blocks
= 4,224 Mbits
8 bit
Page Register
2K Bytes
I/O 0 ~ I/O 7
64 Bytes
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A8
A9
A10
A11
*L
*L
*L
3rd Cycle A12
A13
A14
A15
A16
A17
A18
4th Cycle A20
A21
A22
A23
A24
A25
A26
5th Cycle A28
A29
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
I/O 7
A7
*L
A19
A27
*L
Column Address
Column Address
Row Address
Row Address
Row Address
8
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