KS8695P 查看數據表（PDF） - Micrel

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KS8695P

Integrated Multi-Port PCI Gateway Solution

Micrel 

Micrel, Inc.

KS8695P

Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O) (continued)

Pin

Name

I/O Type(1) Description

P7

DATA[31]

R7

DATA[30]

P8

DATA[29]

R8

DATA[28]

T8

DATA[27]

U8

DATA[26]

P9

DATA[25]

R9

DATA[24]

T9

DATA[23]

U9

DATA[22]

P10

DATA[21]

R10

DATA[20]

T10

DATA[19]

U10

DATA[18]

P11

DATA[17]

R11

DATA[16]

T11

DATA[15]

U11

DATA[14]

P12

DATA[13]

R12

DATA[12]

T12

DATA[11]

U12

DATA[10]

P13

DATA[9]

R13

DATA[8]

T13

DATA[7]

U13

DATA[6]

P14

DATA[5]

R14

DATA[4]

T14

DATA[3]

U14

DATA[2]

T15

DATA[1]

U15

DATA[0]

I/O

External Data Bus. 32-Bit bi-directional data bus for data transfer. The KS8695P

also supports 8-bit and 16-bit data bus widths.

R4

SDCSN[1]

P5

SDCSN[0]

O

SDRAM Chip Select: Active low chip select pins for SDRAM. The KS8695P

supports up to two SDRAM banks. One SDCSN output is provided for each bank.

R5

SDRASN

O

SDRAM Row Address Strobe: Active low. The row address strobe pin for SDRAM.

T5

SDCASN

O

SDRAM Column Address Strobe: Active low. The column address strobe pin for

SDRAM.

U5

SDWEN

O

SDRAM Write Enable: Active low. The write enable signal for SDRAM.

P6

SDQM[3]

R6

SDQM[2]

T6

SDQM[1]

U6

SDQM[0]

O

SDRAM Data Input/Output Mask: Data input/output mask signals for SDRAM. The

SDQM is sampled high and is an output mask signal for write accesses and an

output enable signal for read accesses. Input data are masked during a write cycle.

The SDQM0/1/2/3 correspond to DATA[7:0], DATA[15:8], DATA[23:16] and

DATA[31:24], respectively.

U16

ECSN[2]

T16

ECSN[1]

R16

ECSN[0]

O

External I/O Device Chip Select: Active low. Three external I/O banks are provided

for external memory mapped I/O operations. Each I/O bank stores up to 16KB.

The ECSNx signals indicate which of the three I/O banks is selected.

P16

EWAITN

I

External Wait: Active low. This signal is asserted when an external I/O device or a

ROM/SRAM/FLASH bank needs more access cycles than those defined in the

corresponding control register.

R15

RCSN[1]

P15

RCSN[0]

O

ROM/SRAM/FLASH Chip Select: Active low. The KS8695P can access up to two

external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to

map the CPU addresses into physical memory banks.

Note:

1. I = Input.

O = Output.

I/O = Bidirectional.

May 2006

31

M9999-051806

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