LXT970ATC 查看數據表（PDF） - Intel

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LXT970ATC

Dual-Speed Fast Ethernet Transceiver

Intel 

LXT970A — Dual-Speed Fast Ethernet Transceiver

Table 2. LXT970A MII Signal Descriptions (Continued)

Pin#1

Pin Name

I/O2,3

Signal Description4

Tri-state. In DTE Mode (19.13 = 0), when TRSTE input is High, the LXT970A

isolates itself from the MII Data Interface, and controls the MDIO register bit

0.10 (Isolate bit).

3

TRSTE

I

When MDDIS is High, TRSTE provides continuous control over bit 0.10. When

MDDIS is Low, TRSTE sets initial (default) values only and reverts control back

to the MDIO interface.

In Repeater Mode (19.13 = 1), when TRSTE input is High, the LXT970A tri-

states the receive outputs of the MII (RXD<4:0>, RX_DV, RX_ER, RX_CLK).

MII Control Interface Pins

Management Disable. When MDDIS is High, the MDIO is restricted to Read

Only and the MF<4:0>, CFG<1:0>, and FDE pins provide continual control of

15

MDDIS

I

their respective bits. When MDDIS is Low at power up or Reset, the MF<4:0>,

CFG<1:0>, and FDE pins control only the initial or “default” values of their

respective register bits. After the power-up/reset cycle is complete, bit control

reverts to the MDIO serial channel.

45

MDC

I

Management Data Clock. Clock for the MDIO serial data channel. Maximum

frequency is 2.5 MHz.

44

MDIO

I/O

Management Data Input/Output. Bidirectional serial data channel for PHY/

STA communication.

Full-Duplex Status. When bit 17.1 = 0 (default), this pin indicates full-duplex

status. (High = full-duplex, Low = half-duplex)

This pin can drive a high efficiency LED. (See Table 23 for detail specifications).

2

FDS/MDINT

OD

Management Data Interrupt. When bit 17.1 = 1, an active Low output on this

pin indicates status change.

Interrupt is cleared by sequentially reading Register 1, then Register 18.

1. Pin numbers apply to all package types.

2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.

3. If bit 17.3 = 0, 55Ω series termination resistors are recommended on all output signals to avoid undershoot/overshoot, even

on short traces.

If bit 17.3 = 1, termination resistors are not required.

4. The LXT970A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).

Table 3. LXT970A Fiber Interface Signal Descriptions

Pin#1

Pin Name

I/O2

Signal Description

17

18

FIBOP

FIBON

O

Fiber Output, Positive and Negative. Differential pseudo-ECL driver pair compatible with

standard fiber transceiver for 100BASE-FX.

27

FIBIP

28

FIBIN

I

Fiber Input, Positive and Negative. Differential pseudo-ECL receive pair compatible with

standard fiber transceiver for 100BASE-FX.

1. Pin numbers apply to all package types.

2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.

12

Datasheet

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