LXT970A 查看數據表（PDF） - Intel

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LXT970A

Dual-Speed Fast Ethernet Transceiver

Intel 

Dual-Speed Fast Ethernet Transceiver — LXT970A

Table 7. LXT970A Hardware Control Interface Signal Descriptions (Continued)

Pin#1

Pin Name

I/O2

Signal Description3

Full-Duplex Enable.

When A/N is enabled, FDE determines full-duplex advertisement capability in combination

with MF4 and CFG1.

13

FDE

I When A/N is disabled, FDE directly affects full-duplex operation and determines the value of

bit 0.8 (Duplex Mode).

When FDE is High, full-duplex is enabled and 0.8 = 1.

When FDE is Low, full-duplex is disabled and 0.8 = 0.

Configuration Control 0.

When A/N is enabled, Low-to-High transition on CFG0 causes auto-negotiate to re-start and

0.9 = 1.

14

CFG0

I When A/N is disabled, this input selects operating speed and directly affects bit 0.13.

When CFG0 is High, 100 Mbps is selected and 0.13 = 1. If FX Operation is selected, this

input must be tied High.

When CFG0 is Low, 10 Mbps is selected and 0.13 = 0.

Configuration Control 1.

When A/N is enabled, CFG1 determines operating speed advertisement capabilities in

combination with MF4.

33

CFG1

I When A/N is disabled, CFG1 enables 10 Mbps link test function and directly affects bit 19.8.

When CFG1 is High, 10 Mbps link test is disabled and 19.8 = 1.

When CFG1 is Low, 10 Mbps link test is enabled and 19.8 = 0.

1. Pin numbers apply to all package types.

2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.

3. FDE, CFG0, and CFG1 are affected by the MDDIS input pin. When MDDIS = 0, these inputs determine only the initial state

of the function they control. When MDDIS = 1, these inputs provide continuous hardware control over their corresponding

functions.

Datasheet

15

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