M24512-WMW6T 查看數據表（PDF） - STMicroelectronics
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M24512-WMW6T Datasheet PDF : 24 Pages
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M24512
Table 14. AC Characteristics (M24512 – W)
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock Frequency
400
kHz
tCHCL
tHIGH Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tCH1CH2
tR
Clock Rise Time
300
ns
tCL1CL2
tF
Clock Fall Time
300
ns
tDH1DH2 (2)
tR
SDA Rise Time
20
300
ns
tDL1DL2 (2)
tF
SDA Fall Time
20
300
ns
tDXCX
tSU:DAT Data In Set Up Time
100
ns
tCLDX
tHD:DAT Data In Hold Time
0
ns
tCLQX
tDH
Data Out Hold Time
200
ns
tCLQV (3)
tAA
Clock Low to Next Data Valid (Access Time)
200
900
ns
tCHDX (1)
tSU:STA Start Condition Set Up Time
600
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
tDHDL
tBUF
Time between Stop Condition and Next Start Condition 1300
ns
tW
tWR
Write Time
5 or 10(4)
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. For M24512 devices whose package marking shows the process letter “A” tW(max) = 5ms whereas for M24512 devices whose
package marking shows the process letter “V” tW(max) = 10ms
Table 15. AC Characteristics(1) (M24512 – R)
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
tCHCL
tCLCH
fSCL
tHIGH
tLOW
Clock Frequency
Clock Pulse Width High
Clock Pulse Width Low
400
kHz
600
ns
1300
ns
tDL1DL2 (3)
tF
SDA Fall Time
20
300
ns
tDXCX
tSU:DAT Data In Set Up Time
100
ns
tCLDX
tHD:DAT Data In Hold Time
0
ns
tCLQX
tDH
Data Out Hold Time
200
ns
tCLQV (4)
tAA
Clock Low to Next Data Valid (Access Time)
200
900
ns
tCHDX (2)
tSU:STA Start Condition Set Up Time
600
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
tDHDL
tBUF Time between Stop Condition and Next Start Condition
1300
ns
tW
tWR
Write Time
10
ms
Note: 1. The information contained in Table 15. is related to the new M24512 (process letter “A”) and is subject to change without previous
notice.
2. For a reSTART condition, or following a Write cycle.
3. Sampled only, not 100% tested.
4. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
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