M95512-DR 查看數據表（PDF） - STMicroelectronics

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M95512-DR

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

Operating features

4

Operating features

M95512-W, M95512-R

4.1

4.1.1

4.1.2

4.1.3

Supply voltage (VCC)

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 8 and

Table 10.). This voltage must remain stable and valid until the end of the transmission of the

instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In

order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with

a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package

pins.

Device reset

In order to prevent inadvertent Write operations during power-up, a power-on-reset (POR)

circuit is included. At power-up, the device does not respond to any instruction until VCC has

reached the POR threshold voltage (this threshold is lower than the minimum VCC operating

voltage defined in Table 8 and Table 10).

When VCC passes over the POR threshold, the device is reset and in the following state:

● in the Standby Power mode

● deselected (note that when the device is deselected it is necessary to apply a falling

edge on Chip Select (S) prior to issuing any new instruction, otherwise the instruction is

not executed)

● Status register values:

– the Write Enable Latch (WEL) bit is reset to 0

– the Write In Progress (WIP) bit is reset to 0

– the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).

When VCC passes over the POR threshold, the device is reset and enters the Standby

Power mode, however, the device must not be accessed until VCC reaches a valid and

stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8 and

Table 10.

Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this

time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is

therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see

Figure 4).

In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge

sensitive as well as level sensitive: after power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been high, prior to going low to start the first operation.

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

defined in Table 8 and Table 10 and the rise time must not vary faster than 1 V/µs.

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Doc ID 11124 Rev 13

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