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MAX15038 查看數據表(PDF) - Maxim Integrated

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MAX15038 Datasheet PDF : 19 Pages
First Prev 11 12 13 14 15 16 17 18 19
4A, 2MHz Step-Down Regulator
with Integrated Switches
where the output ripple due to output capacitance,
ESR, and ESL is:
VRIPPLE(C)
=
8
x
IPP
COUT
x
fS
VRIPPLE(ESR) = IPP x ESR
VRIPPLE(ESL)
=
IPP
tON
x ESL
or:
VRIPPLE(ESL)
=
IPP
tOFF
x
ESL
or whichever is larger.
The peak-to-peak inductor current (IP-P) is:
IPP
=
VIN VOUT
fS × L
x
VOUT
VIN
Use these equations for initial output capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output-voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x ΔILOAD. Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor val-
ues. After a short time, the controller responds by regu-
lating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviat-
ing further from its regulating value. See the Compen-
sation Design section for more details.
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The total input capacitance must be
equal or greater than the value given by the following
equation to keep the input-ripple voltage within
specification and minimize the high-frequency ripple
current being fed back to the input source:
CIN _ MIN
=
D x TS x IOUT
VINRIPPLE
where VIN-RIPPLE is the maximum allowed input ripple
voltage across the input capacitors and is recommended
to be less than 2% of the minimum input voltage. D is
the duty cycle (VOUT/VIN) and TS is the switching peri-
od (1/fS).
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
IRIPPLE = ILOAD ×
VOUT × (VIN VOUT )
VIN
where IRIPPLE is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor L and the output capacitor CO. The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
fP1_LC = fP2 _LC =
1
2π x
L
x
CO
x
⎝⎜
RO + ESR
RO + RL
⎠⎟
fZ _ESR
=
2π
1
x ESR
x
CO
where RL is equal to the sum of the output inductor’s DCR
(DC resistance) and the internal switch resistance,
RDS(ON). A typical value for RDS(ON) is 24mΩ (low-side
MOSFET) and 31mΩ (high-side MOSFET). RO is the out-
put load resistance, which is equal to the rated output
voltage divided by the rated output current. ESR is the
total equivalent series resistance of the output capacitor.
If there is more than one output capacitor of the same
type in parallel, the value of the ESR in the above equa-
tion is equal to that of the ESR of a single output capacitor
divided by the total number of output capacitors.
The high switching frequency range of the MAX15038
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer function zero is higher
than the unity-gain crossover frequency, fC, and the zero
cannot be used to compensate for the double pole creat-
ed by the output filtering inductor and capacitor. The dou-
ble pole produces a gain drop of 40dB/decade and a
phase shift of 180°. The compensation network error
14 ______________________________________________________________________________________

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