MB90822 查看數據表（PDF） - Fujitsu

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MB90822

16-bit Proprietary Microcontroller

Fujitsu 

MB90820 Series

(2) Block diagram

Low power mode control register (LPMCR)

STP SLP SPL RST TMD CG1 CG0 RESV

RST Pin

Release reset

Cancel interruption

CPU intermittent

operation selecter

3

Standby control

circuit

Pin high

impedance

control circuit

Pin Hi-z control

Internal reset

generation

circuit

Internal reset

Select intermittent cycles

CPU clock

control circuit

CPU clock

Stop and sleep signals

Stop signal

Clock generator

Clock selector

Machine clock Peripheral clock

Oscillation

control circuit

stabilization waiting

time is passed

Peripheral clock

Oscillation stabilization

3

waiting time interval selector

×1 ×2 ×3 ×4 ×6

PLL multiplier

circuit

2

Reserved MCM WS1 WS0 Reserved MCS CS1 CS0

Clock selection register (CKSCR)

CS2

PLL clock control

register (PCKCR)

X0 Pin

X1 Pin

System clock

generation circuit

Divided

by 2

Divided

by 512

Main clock

Divided

by 2

Divided

by 4

Divided

by 2

Divided

by 2

Timebase timer

31

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