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MN88413

Channel Decoder LSI for Digital Satellite Broadcast Reception

Panasonic Corporation 

MN88413

Digital Bloadcast Reception LSI

s Specifications Overview

• QPSK demodulator

Data rate

: 1 Mbps to 90 Mbps

A/D converter resolution

: 6 bits

Linearity error

: ±0.5 LSB (typical)

Differential linearity error

: ±0.5 LSB (typical)

Input voltage level

: 1.5 V [p-p] (typical) [On-chip self-bias circuit]

Roll-off rate

: Switchable between the DVB and the DSS® specifications.

AFC range

: ± (<symbol rate>/8)

Synchronization establishment time

: 100 ms or less.

D/A converter used for LNB/AFC and AGC

Resolution

: 8 bits

Linearity error

: ±0.5 LSB (typical)

Differential linearity error

: ±0.5 LSB (typical)

Output voltage level

: 1.0 V [p-p] (typical) [0.0 V to 1.0 V]

• Viterbi decoder

: Switchable between the DVB and the DSS® specifications.

: Automatic detection of encoding ratios in the range 1/2 to 7/8.

: Auto-synchronous operation

• Frame synchronization detection, De-interleaver, Reed-Solomon decoding, and Energy dispersal

: Switchable between the DVB and the DSS® specifications.

• PLL circuit

: Reference clock input frequency: 4 MHz to 30 MHz

• CPU interface

: I2C bus interface

• Supply voltage

: 3.3 V ±0.165 V

• Power dissipation : 990 mW (typical) [at VDD = 3.3 V, 60 Mbps, R = 7/8]

• Package

: QFP100-P-1818B (18 × 18 mm)

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