OV7141 查看數據表（PDF） - Unspecified
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OV7141 Datasheet PDF : 20 Pages
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Omni ision
Register Set
Table 5
SCCB Register List
Address Register Default
(Hex)
Name
(Hex)
R/W
Description
Data Format – HSYNC Falling Edge Delay LSB
73
HSDYF
50
RW HSYNCF[9:0] = MSB + LSB = COML[1:0] + HSDYF[7:0]
• Range 000 to 762 pixel delays
74
COMM
20
Common Mode Control M
Bit[7]: Reserved
Bit[6:5]: AGC – Maximum Gain Select
RW
00: +6 dB
01: +12 dB
10: +6 dB
11: +18 dB
Bit[4:0]: Reserved
75
COMN
02
Common Mode Control N
RW
Bit[7]: Output Format – Vertical Flip Enable
Bit[6:0]: Reserved
76
COMO
00
Common Mode Control O
Bit[7:6]: Reserved
Bit[5]: Standby Mode Enable
RW
Bit[4:3]: Reserved
Bit[2]: SCCB – Tri-State Enable – VSYNC, HREF and PCLK
Bit[1:0]: Reserved
77-7D
RSVD
XX
–
Reserved
7E
AVGY
00
RW
AEC – Digital Y/G Channel Average
(Automatically updated by AGC/AEC, user can only read the values)
AEC – Digital R/V Channel Average
7F
AVGR
00
RW (Automatically updated by AGC/AEC, user can only read the values)
Note: This function is not available on the B&W OV7141.
AEC – Digital B/U Channel Average
80
AVGB
00
RW (Automatically updated by AGC/AEC, user can only read the values)
Note: This function is not available on the B&W OV7141.
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
Version 1.4, March 6, 2003
Proprietary to OmniVision Technologies
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