SPHE8200A 查看數據表（PDF） - Unspecified

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产品描述 (功能)

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SPHE8200A

DVD Single Chip MPEG AV Processor

Unspecified 

Preliminary

SPHE8200A

100-110: Available only at 256 pin package

111: Reserved

0xbffe805c sft_cfg6

Description

Pin MUX control register #6 (SDRAM interface control)

l Y Attribute: RW

tia G 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

n O Bit-field

SDQM3 SDQM2 SBA1 SA12 SA11

e L Reset

0

0

0

0

1

1

0

1

1

1

1

1

0

1

1

fid O C SA11

on HN E IN SA12

lus C TEC DIS Y SBA1

unp NIC HAN NL SDQM2

FoSr S&UNMERCUSE O SDQM3

SDRAM address 11 enable

0: SDRAM address 11 is disabled

1: SDRAM address 11 is enabled (default)

SDRAM address 12 enable

0: SDRAM address 12 is disabled

1: SDRAM address 12 is enabled (default)

SDRAM BA1 enable

0: SDRAM BA1 is disabled

1: SDRAM BA1 is enabled (default)

SDRAM DQM2 enable

0: SDRAM DQM2 is disabled

1: SDRAM DQM2 is enabled (default)

SDRAM DQM3 enable

0: SDRAM DQM3 is disabled

1: SDRAM DQM3 is enabled (default)

0

1

© Sunplus Technology Co., Ltd.

37

Proprietary & Confidential

OCT. 07, 2003

Preliminary Version: 0.2

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