XRT91L81 查看數據表（PDF） - Exar Corporation

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XRT91L81

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

PRELIMINARY

RECEIVER SECTION

NAME

LEVEL

TYPE

RXI0P

RXI0N

CMLDIFF

I

RXI1P

RXI1N

CMLDIFF

I

RXSEL

LVTTL

I

REXT

-

I

RXCLK16P

LVDS

O

RXCLK16N

LOCKDET_CDR

LVTTL

O

LOSEXT

LVTTL

I

POLARITY

LVTTL

I

LOSDET

LVTTL

O

DISRD

LVTTL

I

XRT91L81

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

REV. P1.0.3

PIN

DESCRIPTION

C1 Primary Receive Serial Data Input

D1 The receive serial data stream of 2.488Gbps is applied to the

primary input pins if RXSEL is "Low". In Forward Error Correc-

tion, the receive serial data stream is 2.666Gbps.

G1 Secondary Receive Serial Data Input Port

F1 The receive serial data stream of 2.488Gbps is applied to the

secondary input pins if RXSEL is "High". In Forward Error Cor-

rection, the receive serial data stream is 2.666Gbps.

A2 Receive Serial Data Select

Hardware Mode This pin is used to select the Receive Serial

Data Input from the primary or secondary inputs.

"Low" = RXI0

"High" = RXI1

A1 Limiting Amplifier Biasing Resistor

This pin should be pulled "Low" with a 499Ω resistor.

A6 155.52 (166) MHz Reference Clock

A7 This output clock reference is derived from the recovered clock

from the receive path.

C7 CDR Lock Detect

This pin will be pulled "High" to indicate that the CDR is locked.

B5 LOS or SD input from optical module

C4 Polarity for LOS input

Hardware Mode LOSEXT and POLARITY signals will be

Exclussive NORed internally to generate the correct polarity.

C5 LOS Detect

Flags LOS condition based on LOS/SD signal from optical

module.

A3 Disable Receive Output Data Upon LOS

Hardware Mode If this pin is pulled "High", the receive output

data will automically pull "Low" when a LOS condition occurs.

"Low" = Disabled

"High" = Mute Data Upon LOS

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