M95040-RDW3T/S 查看數據表（PDF） - STMicroelectronics

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M95040-RDW3T/S

4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock - Compatible with SPI Bus Serial Interface

STMicroelectronics 

Instructions

6

Instructions

M95040, M95020, M95010

Each instruction starts with a single-byte code, as summarized in Table 4.

If an invalid instruction is sent (one not contained in Table 4), the device automatically

deselects itself.

Table 4. Instruction set

Instruction

Description

Instruction Format

WREN

Write Enable

0000 X110(1)

WRDI

Write Disable

0000 X100(1)

RDSR

Read Status Register

0000 X101(1)

WRSR

Write Status Register

0000 X001(1)

READ

WRITE

Read from Memory Array

Write to Memory Array

0000 A8011(2)

0000 A8010(2)

1. X = Don’t Care.

2. A8 = 1 for the upper half of the memory array of the M95040, and 0 for the lower half, and is Don’t Care for

other devices.

6.1

Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven Low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then

enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven

High.

Figure 7. Write Enable (WREN) sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI01441D

16/42

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