M95040-RDW3TPW 查看數據表（PDF） - STMicroelectronics

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M95040-RDW3TPW

4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock - Compatible with SPI Bus Serial Interface

STMicroelectronics 

M95040, M95020, M95010

Instructions

6.2

Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction

to the device.

As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select

(S) being driven High.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

● Power-up

● WRDI instruction execution

● WRSR instruction completion

● WRITE instruction completion

● Write Protect (W) line being held Low.

Figure 8. Write Disable (WRDI) sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03790D

17/42

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