MAX19700 查看數據表（PDF） - Maxim Integrated

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MAX19700

7.5Msps, Ultra-Low-Power Analog Front-End

Maxim Integrated 

7.5Msps, Ultra-Low-Power

Analog Front-End

Table 2. Tx Path Output Voltage vs. Input Codes

(Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN; VFS = 410mV for

820mVP-P Full Scale and VFS = 500mV for 1VP-P Full Scale)

DIFFERENTIAL OUTPUT VOLTAGE (V)

( ) VFS

VREFDAC × 1023

1024 1023

( ) VFS

VREFDAC

1024

× 1021

1023

OFFSET BINARY (D0–D9)

11 1111 1111

11 1111 1110

INPUT DECIMAL CODE

1023

1022

( ) VFS

VREFDAC

1024

×3

1023

10 0000 0001

513

( ) VFS

VREFDAC

1024

×1

1023

10 0000 0000

512

( ) VFS

−VREFDAC × 1

1024 1023

01 1111 1111

511

( ) VFS

−VREFDAC × 1021

1024 1023

00 0000 0001

1

( ) VFS

−VREFDAC × 1023

1024 1023

00 0000 0000

0

CLK

D0–D9

ID

tDSQ

Q: N - 2

I: N - 1

tDSI

tDHQ

Q: N - 1

I: N

Q: N

tDHI

N-2

N-1

I: N + 1

N

QD

N-2

N-1

N

Figure 5. Tx DAC System Timing Diagram

Tx DAC Timing

Figure 5 shows the relationship between the clock, input

data, and analog outputs. Data for the I-channel (ID) is

latched on the falling edge of the clock signal, and Q-

channel (QD) data is latched on the rising edge of the

clock signal. Both I and Q outputs are simultaneously

updated on the next rising edge of the clock signal.

3-Wire Serial Interface and

Operation Modes

The 3-wire serial interface controls the MAX19700 oper-

ation modes as well as the three 12-bit aux-DACs. Upon

power-up, program the MAX19700 to operate in the

desired mode. Use the 3-wire serial interface to pro-

gram the device for shutdown, idle, standby, Rx, Tx, or

aux-DAC modes. A 16-bit data register sets the mode

control. The 16-bit word is comprised of A3–A0 control

bits and D11–D0 data bits. Tables 4, 5, and 6 show the

MAX19700 operating modes and SPI commands. The

serial interface remains active in all modes.

18 ______________________________________________________________________________________

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