MAX17410EVKIT 查看數據表（PDF） - Maxim Integrated

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MAX17410EVKIT

MAX17410 Evaluation Kit

Maxim Integrated 

MAX17410 Evaluation Kit

Setting the Output Voltage

The MAX17410 has an internal digital-to-analog con-

verter (DAC) that programs the output voltage. The out-

put voltage can be digitally set from 0 to 1.5000V

(Table 2) from the D0–D6 pins. There are two different

ways of setting the output voltage:

1) Drive the external VID0–VID6 inputs (all SW1 posi-

tions are off). The output voltage is set by driving

VID0–VID6 with open-drain drivers (pullup resistors

are included on the board) or 3V/5V CMOS output

logic levels.

2) Switch SW1. When SW1 positions are off, the

MAX17410’s D0–D6 inputs are at logic 1 (connect-

ed to VDD). When SW1 positions are on, D0–D6

inputs are at logic 0 (connected to GND). The out-

put voltage can be changed during operation by

activating SW1 on and off. As shipped, the EV kit is

configured with SW1 positions set for 0.9750V out-

put (Table 2). Refer to the MAX17410 IC data sheet

for more information.

Table 1. MAX17410 Operating Mode Truth Table Functions

SHDN

SW2

(1, 10)

INPUTS

DPRSTP DPRSLPVR

SW2

SW2

(5, 6)

(2, 9)

PSI

SW2

(3, 8)

PHASE

OPERATION*

OPERATING MODE

GND

X

X

X

Disabled

Low-Power Shutdown Mode. DL1 and DL2 are forced

low and the controller is disabled. The supply current

drops to 1µA (max).

Rising

X

Startup/Boot. When SHDN is pulled high, the MAX17410

X

X

Multiphase Forced-PWM begins the startup sequence. Once the REF is above

1/8 RTIME Slew Rate 1.84V, the controller enables the PWM controller and

ramps the output voltage up to the boot voltage.

High

X

High

X

High

Low

High

High

Low

Low

High

High

High

Low

X

X

Multiphase Forced-PWM

Nominal RTIME Slew Rate

1-Phase Forced-PWM

Nominal RTIME Slew Rate

1-Phase Pulse Skipping

Nominal RTIME Slew Rate

1-Phase Pulse Skipping

1/4 RTIME Slew Rate

Full Power. The no-load output voltage is determined by

the selected VID DAC code (D0–D6, Table 2).

Intermediate Power. The no-load output voltage is

determined by the selected VID DAC code (D0–D6,

Table 2). When PSI is pulled low, the MAX17410

immediately disables phase 2. DH2 and DL2 are pulled

low.

Deeper Sleep Mode. The no-load output voltage is

determined by the selected VID DAC code (D0–D6,

Table 2). When DPRSLPVR is pulled high, the

MAX17410 immediately enters 1-phase pulse-skipping

operation allowing automatic PWM/PFM switchover

under light loads. The PWRGD and CLKEN upper

thresholds are blanked. DH2 and DL2 are pulled low.

Deeper Sleep Slow Exit Mode. The no-load output

voltage is determined by the selected VID DAC code

(D0–D6, Table 2). When DPRSTP is pulled high while

DPRSLPVR is already high, the MAX17410 remains in 1-

phase pulse-skipping operation allowing automatic

PWM/PFM switchover under light loads. The PWRGD

and CLKEN upper thresholds are blanked. DH2 and DL2

are pulled low.

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