MAX17410EVKIT 查看數據表（PDF） - Maxim Integrated

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MAX17410EVKIT

MAX17410 Evaluation Kit

Maxim Integrated 

MAX17410 Evaluation Kit

Reduced Power-Dissipation

Voltage Positioning

The MAX17410 includes a transconductance amplifier

for adding gain to the voltage-positioning sense path.

The amplifier’s input is generated by summing the cur-

rent-sense inputs, which differentially sense the voltage

across the inductor’s DCR. The transconductance

amplifier’s output connects to the voltage-positioned

feedback input (FB), so the resistance between FB and

VPS (R4) determines the voltage-positioning gain.

Resistor R4 (4.75kΩ) provides a -2.1mV/A voltage-posi-

tioning slope at the output when all phases are active.

Remote output and ground sensing eliminate any addi-

tional PCB voltage drops.

Dynamic Output-Voltage

Transition Experiment

This MAX17410 EV kit is set to transition the output volt-

age at 12.5mV/µs. The speed of the transition is altered

by scaling resistors R2 and R3.

During the voltage transition, watch the inductor current

by looking at the current-sense inputs with a differential

scope probe. Observe the low, well-controlled inductor

current that accompanies the voltage transition. Slew-rate

control during shutdown and startup results in well-con-

trolled currents in to and out of the battery (input source).

There are two methods to create an output-voltage tran-

sition. Select D0–D6 (SW1). Then either manually

change the SW1 settings to a new VID code setting

(Table 2), or disable all SW1 settings and drive the

VID0–VID6 PCB test points externally to the desired

code settings.

Switch SW2 Settings

Shutdown SW2 (1, 10)

When SHDN goes low (SW2 (1, 10) = on), the

MAX17410 enters the low-power shutdown mode.

PWRGD is pulled low immediately, and the output volt-

age ramps down at 1/8 the slew rate set by R2 and R3

(71.9kΩ). When the controller reaches the 0V target, the

drivers are disabled (DL1 and DL2 driven high), the ref-

erence is turned off, and the IC supply currents drop to

1µA (max).

When a fault condition activates the shutdown

sequence (output undervoltage lockout or thermal shut-

down), the protection circuitry sets the fault latch to pre-

vent the controller from restarting. To clear the fault

latch and reactivate the MAX17410, toggle SHDN or

cycle VDD power. Table 3 shows the shutdown mode

(SHDN).

Table 3. Shutdown Mode (SHDN)

SW2 (1, 10) SHDN PIN

MAX17410 OUTPUT

Off

Connected

to VDD

Output enabled—VOUT is

selected by VID DAC code

(D0–D6) settings

On

Connected

to GND

Shutdown mode, VOUT = 0V

DPRSLPVR SW2 (2, 9), PSI SW2 (3, 8)

DPRSLPVR and PSI together determine the operating

mode, as shown in Table 4. The MAX17410 will be

forced into full-phase PWM mode during startup, while

in boot mode, during the transition from boot mode to

VID mode, and during shutdown.

DPRSTP SW2 (5,6)

The DPRSTP logic signal is usually the logical comple-

ment of the DPRSLPVR signal. However, there is a spe-

cial condition when both DPRSTP and DPRSLPVR

could temporarily be simultaneously high. If this hap-

pens, the slew rate reduces to 1/4 of the normal (RTIME-

based) slew rate for the duration of this condition. The

slew rate returns to normal when this condition is exit-

ed. Note: Only DPRSLPVR and PSI (not DPRSTP)

determine the mode of operation (PWM vs. skip and the

number of active phases). See Table 5.

Table 4. DPRSLPVR, PSI

DPRSLPVR

PSI

SW2 (2, 9) SW2 (3, 8)

POWER

LEVEL

OPERATING

MODE

On (VDD) On (GND)

Very low 1-phase pulse-

current skipping mode

On (VDD)

Off (VDD)

Low current 1-phase pulse-

(3A)

skipping mode

Off (GND) On (GND) Intermediate 1-phase forced-

PWM mode

Off (GND) Off (VDD)

Maximum

Normal

operation—all

phases are active,

forced-PWM mode

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