AD8176-EVAL(2007) 查看數據表（PDF） - Analog Devices
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AD8176-EVAL Datasheet PDF : 32 Pages
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Preliminary Technical Data
AD8176
TIMING CHARACTERISTICS (SERIAL MODE)
Table 2.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to SEROUT Valid
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RST Time
Specifications subject to change without notice.
t2
1
CLK
0
1
SERIN
0
t1
t3
OUT8 (D4)
1 = LATCHED
UPDATE
0 = TRANSPARENT
t7
Symbol
Min
t1
40
t2
60
t3
50
t4
140
t5
10
t6
90
t7
120
9
t4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
Limit
Typ
Max
TBD
TBD
TBD
OUT8 (D3)
OUT00 (D0)
t5
t6
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
SEROUT
Table 3. Logic Levels, VDD = 3.3 V
VIH
VIL
VOH
SER/PAR, CLK, SER/PAR, CLK, SEROUT
SERIN, UPDATE SERIN, UPDATE
2.0 V min
0.6 V max
2.8 V min
Figure 2. Timing Diagram, Serial Mode
VOL
SEROUT
0.4 V max
IIH
SER/PAR, CLK,
SERIN, UPDATE
20 μA max
IIL
SER/PAR, CLK,
SERIN, UPDATE
–20 μA max
IOH
SEROUT
–1 mA min
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
IOL
SEROUT
1 mA min
Table 4. H and V Logic Levels, VDD = 3.3 V
VOH
VOL
2.7 V min
0.5 V max
IOH
–3 mA max
IOL
3 mA max
Table 5. RST Logic Levels, VDD = 3.3 V
VIH
VIL
2.0 V min
0.6 V max
IIH
−60 μA max
IIL
−120 μA max
Table 6. CSB Logic Levels, VDD = 3.3 V
VOH
VOL
2.0 V min
0.6 V max
IIH
100 μA max
Rev. PrA | Page 5 of 32
IOL
40 μA max
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