AD7440BRTZ-R22 查看數據表（PDF） - Analog Devices

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AD7440BRTZ-R22

Differential Input, 1 MSPS 10-Bit and 12-Bit ADCs in an 8-Lead SOT-23

Analog Devices 

AD7440/AD7450A

Example 1

VIN max = VDD + 0.3

VIN max = VREF + VREF/2

If VDD = 5 V, then VIN max = 5.3 V.

Therefore

3 × VREF/2 = 5.3 V

VREF max = 3.5 V

Thus, when operating at VDD = 5 V, the value of VREF can range

from 100 mV to a maximum value of 3.5 V. When VDD = 4.75 V,

VREF max = 3.17 V.

Example 2

VIN max = VDD + 0.3

VIN max = VREF + VREF/2

If VDD = 3 V, then VIN max = 3.3 V.

Therefore,

3 × VREF/2 = 3.3 V

VREF max = 2.2 V

Thus, when operating at VDD = 3 V, the value of VREF can range

from 100 mV to a maximum value of 2.2 V. When VDD = 2.7 V,

VREF max = 2 V.

These examples show that the maximum reference applied to

the AD7440/AD7450A is directly dependent on the value

applied to VDD.

The value of the reference sets the analog input span and the

common-mode voltage range. Errors in the reference source

result in gain errors in the AD7440/AD7450A transfer function

and add to specified full-scale errors on the part. A 0.1 μF

capacitor should be used to decouple the VREF pin to GND.

Figure 38 shows a typical connection diagram for the VREF pin.

Table 6 lists examples of suitable voltage references.

VDD

0.1μF

10nF

AD780

NC

0.1μF

1

OPSEL 8 NC

2 VIN

7 NC

3 TEMP VOUT 6 2.5V

4 GND TRIM 5 NC

NC = NO CONNECT

VDD

AD7440/

AD7450A*

VREF

0.1μF

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 38. Typical VREF Connection Diagram for VDD = 5 V

Table 6. Examples of Suitable Voltage References

Output

Initial

Operating

Reference Voltage (V) Accuracy (%) Current (μA)

AD780

2.5/3

0.04

1000

ADR421

2.5

0.04

500

ADR420

2.048

0.05

500

SINGLE-ENDED OPERATION

When supplied with a 5 V power supply, the AD7440/AD7450A

can handle a single-ended input. The design of these devices is

optimized for differential operation, so with a single-ended

input, performance degrades. Linearity degrades by typically

0.2 LSB, the full-scale errors degrade typically by 1 LSB, and ac

performance is not guaranteed.

To operate the AD7440/AD7450A in single-ended mode, the

VIN+ input is coupled to the signal source, while the VIN– input is

biased to the appropriate voltage corresponding to the midscale

code transition. This voltage is the common mode, which is a

fixed dc voltage (usually the reference). The VIN+ input swings

around this value and should have a voltage span of 2 × VREF to

make use of the full dynamic range of the part. The input signal

therefore has peak-to-peak values of common mode ±VREF. If

the analog input is unipolar, an op amp in a noninverting unity

gain configuration can be used to drive the VIN+ pin. The ADC

operates from a single supply, so it is necessary to level shift

ground-based bipolar signals to comply with the input

requirements. An op amp can be configured to rescale and level

shift the ground-based bipolar signal, so it is compatible with

the selected input range of the AD7440/AD7450A (Figure 39).

+2.5V

0V

–2.5V

R

VIN

R

R

5V

R

2.5V

0V

0.1μF

VIN+

AD7440/

AD7450A

VIN–

VREF

EXTERNAL

VREF (2.5V)

Figure 39. Applying a Bipolar Single-Ended Input to the AD7440/AD7450A

Rev. C | Page 20 of 28

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