AD7453 查看數據表（PDF） - Analog Devices

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AD7453

Pseudo Differential, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23

Analog Devices 

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7453 when not con-

verting, the average power consumption of the ADC decreases

at lower throughput rates. Figure 27 shows how, as the through-

put rate is reduced, the device remains in its power-down state

longer and the average power consumption reduces accordingly.

For example, if the AD7453 is operated in continuous sampling

mode with a throughput rate of 100 kSPS and a 10 MHz SCLK,

and the device is placed in the power-down mode between con-

versions, then the power consumption is calculated as follows:

Power dissipation during normal operation = 7.25 mW max (for

VDD = 5 V).

If the power-up time is one dummy cycle (1.06 µs if CS is

brought high after the 10th SCLK falling edge in the cycle and

then brought low after the quiet time) and the remaining

conversion time is another cycle (1.6 µs), then the AD7453 can

be said to dissipate 7.25 mW for 2.66 µs∗ during each

conversion cycle.

If the throughput rate = 100 kSPS, then the cycle time = 10 µs

and the average power dissipated during each cycle is

(2.66/10) × 7.25 mW = 1.92 mW

For the same scenario, if VDD = 3 V, the power dissipation during

normal operation is 3.3 mW max. The AD7453 can now be said

to dissipate 3.3 mW for 2.66 µs∗ during each conversion cycle.

The average power dissipated during each cycle with a

throughput rate of 100 kSPS is therefore

(2.66/10) × 3.3 mW = 0.88 mW

This is how the power numbers in Figure 27 are calculated.

100

10

VDD = 5V

1

VDD = 3V

0.1

0.01

0

50

100

150

200

250

300

350

THROUGHPUT (kSPS)

Figure 27. Power vs. Throughput Rate for Power-Down Mode

AD7453

For throughput rates above 320 kSPS, the serial clock frequency

should be reduced for optimum power performance.

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7453 allows the part to be con-

nected directly to a range of different microprocessors. This

section explains how to interface the AD7453 with some of the

more common microcontroller and DSP serial interface

protocols.

AD7453 to ADSP-21xx

The ADSP-21xx family of DSPs are interfaced directly to the

AD7453 without any glue logic required.

The SPORT control register should be set up as follows:

TFSW = RFSW = 1

INVRFS = INVTFS = 1

DTYPE = 00

SLEN = 1111

ISCLK = 1

TFSR = RFSR = 1

IRFS = 0

ITFS = 1

Alternate Framing

Active Low Frame Signal

Right Justify Data

16-Bit Data-Words

Internal Serial Clock

Frame Every Word

To implement power-down mode, SLEN should be set to 1001

to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 28. The ADSP-21xx

has the TFS and RFS of the SPORT tied together, with TFS set

as an output and RFS set as an input. The DSP operates in

alternate framing mode and the SPORT control register is set

up as described. The frame synchronization signal generated on

the TFS is tied to CS, and, as with all signal processing applica-

tions, equidistant sampling is necessary. However, in this

example, the timer interrupt is used to control the sampling rate

of the ADC, and, under certain conditions, equidistant sampling

may not be achieved.

AD7453*

ADSP-21xx*

SCLK

SDATA

CS

SCLK

DR

RFS

TFS

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 28. Interfacing to the ADSP-21xx

∗This figure assumes a very short time to enter power-down mode. This

increases as the burst of clocks used to enter power down mode is

increased.

Rev. B | Page 17 of 20

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