OR2C10A3S208I-DB 查看數據表（PDF） - Lattice Semiconductor
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OR2C10A3S208I-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Programmable Logic Cells (continued))
Data Sheet
November 2006
CARRY
COUT
A4
A3
A2
S A1
E A0
IC B4
V D B3
E B2
B1
E U B0
D IN CIN
C0
LSR
T GSR
T WD[3:0]
CK
C CKEN
N TRI
A4
A3
QLUT3
A2
A1
CARRY
A3
A2
QLUT2
A1
A0
A4
CARRY
B4
B3
QLUT1
B2
B1
CARRY
B3
B2
QLUT0
B1
B0
B4
PFU_NAND
F3
C
WD3
F2
C
WD2
PFU_MUX
PFU_XOR
F1
C
WD1
F0
C
WD0
CC
D3
Q3
REG3
SR EN
D2
Q2
REG2
C
SR EN
D1
Q1
REG1
SR EN
D0
Q0
REG0
SR EN
C
C
E O Key: C = controlled by configuration RAM.
Figure 3. Simplified PFU Diagram
O4
O3
O2
O1
O0
T
T
T
T
C
T
T
T
T
C
5-4573(F)
EL C Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The ports
are referenced with a two- to four-character suffix to a
S IS PFU’s location. As mentioned, there are two 5-bit input
data buses (A[4:0] and B[4:0]) to the LUT, one 4-bit
input data bus (WD[3:0]) to the latches/FFs, and an
D output data bus (O[4:0]).
found in each PLC are also shown, although they actu-
ally reside external to the PFU.
Each latch/FF can accept data from the LUT. Alterna-
tively, the latches/FFs can accept direct data from
WD[3:0], eliminating the LUT delay if no combinatorial
function is needed. The LUT outputs can bypass the
latches/FFs, which reduces the delay out of the PFU. It
Figure 3 shows the four latches/FFs (REG[3:0]) and the is possible to use the LUT and latches/FFs more or
64-bit look-up table (QLUT[3:0]) in the PFU. The PFU
less independently. For example, the latches/FFs can
does combinatorial logic in the LUT and sequential
be used as a 4-bit shift register, and the LUT can be
logic in the latches/FFs. The LUT is static random
used to detect when a register has a particular pattern
access memory (SRAM) and can be used for read/
in it.
write or read-only memory. The eight 3-state buffers
8
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