AD74111 查看數據表（PDF） - Analog Devices
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AD74111 Datasheet PDF : 20 Pages
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AD74111
there will be a fixed relationship between the instruction cycle
time of the DSP program and the AD74111, so a timer could be
used to accurately control the DAC updates. If a timer is not
available, the Multiframe-Sync (MFS) mode could be used to
generate a DFS pulse every 16 or 32 DCLKs, allowing the DSP
to accurately control the number of DCLKs between updates
using an autobuffering or DMA type technique. In all cases for
Slave mode operation, there should be 128 DCLKs (Normal
mode) or 256 DCLKs (Fast mode) between DAC updates. The
ADC operates in a similar manner; however, if the DSP does not
read an ADC result, this will appear only as a missed sample and
will not be audible. Slave mode is most suited to state-machine
type applications where the number of DCLKs and their
relationships to the other interface signals can be controlled.
Table II. Serial Mode Selection
CRD:2 CRC:5, 4
CRD:3 DSP Word Operating
DM/MM Mode Width Mode
Figure
0
0
16
16-Bit Data Mode 15
0
1
16
32-Bit Data Mode 19
1
0
16
16-Bit Mixed Mode 13
1
1
16
32-Bit Mixed Mode 17
0
0
>16
16-Bit Data Mode 16
0
1
>16
32-Bit Data Mode 20
1
0
>16
16-Bit Mixed Mode 14
1
1
>16
32-Bit Mixed Mode 18
1/fS
CONTROL
DAC
DIN
(16 BITS) (16 BITS)
CONTROL
DAC
(16 BITS) (16 BITS)
DOUT
SSTTAATTUUSS
ADC
(16 BITS) (16 BITS)
SSTTAATTUUSS
ADC
((1166 BBIITTSS)) (16 BITS)
DFS
(MM16)
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 13. 16-Bit Mixed Mode, Word Length = 16 Bits
1/fS
CONTROL
DIN
(16 BITS)
DAC DATA
(24 BITS)
DOUT
STATUS
(16 BITS)
ADC DATA
(24 BITS)
DFS
(MM16)
16 DCLKS
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 14. 16-Bit Mixed Mode, Word Length = 24 Bits
CONTROL
(16 BITS)
STATUS
(16 BITS)
1/fS
DAC
DIN
(16 BITS)
DAC
(16 BITS)
DOUT
STAADTCUS
(16 BITS)
STAADTCUS
((1166 BBIITTSS))
DFS
(MM16)
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 15. 16-Bit Data Mode, Word Length = 16 Bits
–12–
REV. 0
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