AD7478ART 查看數據表（PDF） - Analog Devices
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AD7478ART Datasheet PDF : 20 Pages
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AD7476/AD7477/AD7478
–50
–55
–60
–65
VDD = 2.35V
–70
VDD = 5.25V
VDD = 2.7V
–75
–80
–85
–90
10k
VDD = 4.75V
VDD = 3.6V
100k
1M
INPUT FREQUENCY – Hz
Figure 9. THD vs. Analog Input Frequency, fS = 993 kSPS
–72
VDD = 2.35V
–74
–76
–78
VDD = 2.7V
–80
VDD = 4.75V
VDD = 5.25V
–82
VDD = 3.6V
–84
10k
100k
1M
INPUT FREQUENCY – Hz
Figure 10. THD vs. Analog Input Frequency, fS = 605 kSPS
Digital Inputs
The digital inputs applied to the AD7476/AD7477/AD7478 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the VDD + 0.3 V limit as on the analog inputs. For
example, if the AD7476/AD7477/AD7478 were operated with a
VDD of 3 V, then 5 V logic levels could be used on the digital
inputs. However, it is important to note that the data output on
SDATA will still have 3 V logic levels when VDD = 3 V. Another
advantage of SCLK and CS not being restricted by the VDD +
0.3 V limit is the fact that power supply sequencing issues are
avoided. If CS or SCLK is applied before VDD, there is no risk of
latch-up as there would be on the analog inputs if a signal greater
than 0.3 V was applied prior to VDD.
MODES OF OPERATION
The mode of operation of the AD7476/AD7477/AD7478 is
selected by controlling the (logic) state of the CS signal during a
conversion. There are two possible modes of operation, Normal
mode and Power-Down mode. The point at which CS is pulled
high after the conversion has been initiated will determine whether
or not the AD7476/AD7477/AD7478 will enter Power-Down
mode. Similarly, if already in power-down, CS can control
whether the device will return to normal operation or remain in
power-down. These modes of operation are designed to provide
flexible power management options. These options can be chosen
to optimize the power dissipation/throughput rate ratio for different
application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance,
as the user does not have to worry about any power-up times
with the AD7476/AD7477/AD7478 remaining fully powered all
the time. Figure 11 shows the general diagram of the operation
of the AD7476/AD7477/AD7478 in this mode.
The conversion is initiated on the falling edge of CS as described
in the Serial Interface section. To ensure the part remains fully
powered up at all times, CS must remain low until at least 10
SCLK falling edges have elapsed after the falling edge of CS. If
CS is brought high any time after the tenth SCLK falling edge,
but before the sixteenth SCLK falling edge, the part will remain
powered up but the conversion will be terminated and SDATA
will go back into three-state. Sixteen serial clock cycles are
required to complete the conversion and access the complete
CS
1
SCLK
10
16
SDATA
4 LEADING ZEROS + CONVERSION RESULT
Figure 11. Normal Mode Operation
CS
SCLK
SDATA
12
10
16
THREE-STATE
Figure 12. Entering Power-Down Mode
–12–
REV. D
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