OKL2-T/3-W12P-C 查看數據表（PDF） - Murata Power Solutions

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OKL2-T/3-W12P-C

Programmable Output 3-Amp iLGA SMT PoLs

Murata Power Solutions 

Window

Comparator

Common

External

+Logic Supply

(+5V max.)

Power

Good

5mA max.

User’s External

Logic

–Vin

Power

Output

Logic

Ground

HI impedance (Open Drain) = Power Ok

LO impedance (Saturation) = Power Not Ok

Figure 6. Power Good Circuit

Output Voltage Sequencing

The OKL modules include a sequencing feature that enables users to

implement various types of output voltage sequencing in their applications.

This is accomplished via an additional sequencing pin. When not using the

sequencing feature, either tie the sequence pin to Vin or leave it uncon-

nected.

When an analog voltage is applied to the sequence pin, the output

voltage tracks this voltage until the output reaches the set-point voltage.

The final value of the sequence voltage must be set higher than the set-

point voltage of the module. The output voltage follows the voltage on the

sequence pin on a one-to-one volt basis. By connecting multiple modules

together, multiple modules can track their output voltages to the voltage

applied on the sequence pin.

For proper voltage sequencing, first, input voltage is applied to the

module. The On/Off pin of the module is left unconnected (or tied to GND

for negative logic modules or tied to Vin for positive logic modules) so that

the module is ON by default. After applying input voltage to the module,

a minimum 10msec delay is required before applying voltage on the

sequence pin. During this time, a voltage of 50mV (± 20 mV) is maintained

on the sequence pin. This delay gives the module enough time to complete

its internal powerup soft-start cycle. During the delay time, the sequence

pin should be held close to ground (nominally 50mV ± 20 mV). This is re-

quired to keep the internal opamp out of saturation thus preventing output

overshoot during the start of the sequencing ramp. By selecting resistor R1

according to the following equation

R1 = —2—35—00— ohms,

Vin – 0.05

the voltage at the sequencing pin will be 50mV when the sequencing

signal is at zero. See figure 7 for R1 connection for the sequencing signal to

the SEQ pin.

hCtltipc:k//whwerwe.mtourvaietaw-pAs.pcpolmic/adtaiotan/aNponoteteDs/CdAcaNn--6611.pdf

OKL-T/3-W12 Series

Programmable Output 3-Amp iLGA SMT PoLs

+Vin

OKL -T

470K

R1

SEQ

Control Voltage

SEQ

10K

+

OUT

–

GND

Figure 7. Sequencing Signal Interface of Module

Voltage Range Graph

Please observe the limits below for voltage input and output ranges. These

limits apply at all output currents.

16

14

12

10

8

Vin=4.5V / Vout=3.63V

6

Vin=14V / Vout=1V

4

Upper Limit

2

Lower Limit

0

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

Output Voltage (V)

Output Current Limiting

Current limiting inception is defined as the point at which full power falls

below the rated tolerance. See the Performance/Functional Specifica-

tions. Note particularly that the output current may briefly rise above its

rated value in normal operation as long as the average output power is

not exceeded. This enhances reliability and continued operation of your

application. If the output current is too high, the converter will enter the

short circuit condition.

Output Short Circuit Condition

When a converter is in current-limit mode, the output voltage will drop

as the output current demand increases. If the output voltage drops too

low (approximately 98% of nominal output voltage for most models), the

magnetically coupled voltage used to develop PWM bias voltage will also

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MDC_OKL-T/3-W12 Series.C02 Page 15 of 17

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