RTL8211E-VB-CG 查看數據表（PDF） - Realtek Semiconductor

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RTL8211E-VB-CG

INTEGRATED 10/100/1000M ETHERNET TRANSCEIVER

Realtek Semiconductor 

RTL8211E/RTL8211EG

Datasheet

Symbol

TGCC

Duty_G

Duty_T

tR

tF

TsetupT

TholdT

TsetupR

TholdR

TskewT

TskewR

Table 65. RGMII Timing Parameters

Description

Min

Clock Cycle Duration (Giga)

7.2

Clock Cycle Duration (100Mbps)

36

Clock Cycle Duration (10Mbps)

360

Duty Cycle for Gigabit

45

Duty Cycle for 10/100T

40

RXC Rise Time (20%~80%)

-

RXC Fall Time (20%~80%)

-

Data to Clock Output Setup (at transmitter

1.2

integrated delay)

Data to Clock Output Hold (at transmitter

1.2

integrated delay)

Data to Clock Input Setup (at receiver integrated

1.0

delay)

Data to Clock Input Hold (at receiver integrated

1.0

delay)

Data to Clock Output Skew (at transmitter)

-0.5

Data to Clock Input Skew (at receiver)

1

This implies that PC board design will require

clocks to be routed such that an additional trace

delay of greater than 1.5ns and less than 2.0ns

will be added to the associated clock signal.

Typical

8

40

400

50

50

-

-

2

2

2

2

0

1.8

Max

Units

8.8

ns

44

ns

440

ns

55

%

60

%

0.75

ns

0.75

ns

-

ns

-

ns

-

ns

-

ns

0.5

ns

2.6

ns

Integrated 10/100/1000M Ethernet Transceiver

65

Track ID: JATR-3375-16 Rev. 1.6

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