1417H5 查看數據表（PDF） - Agere -> LSI Corporation

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1417H5

NetLight® 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery

Agere -> LSI Corporation 

NetLight 1417G5 and 1417H5-Type

ATM/SONET/SDH Transceivers with Clock Recovery

Data Sheet

January 2000

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Parameter

Supply Voltage

Operating Case Temperature Range

Storage Case Temperature Range

Lead Soldering Temperature/Time

Operating Wavelength Range

Symbol

Min

Max

Unit

VCC

0

3.6

V

TC

–40

85

°C

Tstg

–40

85

°C

—

—

250/10

°C/s

λ

1.1

1.6

nm

Pin Information

TX

20 19 18 17 16 15 14 13 12 11

20-PIN MODULE - TOP VIEW

1 2 3 4 5 6 7 8 9 10

RX

Figure 1. 1417G5 and 1714H5 Transceivers, 20-Pin Configuration, Top View

1-967(F).b

Table 1. Transceiver Pin Descriptions

Pin

Number

MS

1

2

3

4

5

6

7

8

9

10

Symbol

Name/Description

MS

Photode-

tector Bias

VEER

VEER

CLK–

CLK+

VEER

VCCR

SD

RD–

RD+

Receiver

Mounting Studs. The mounting studs are provided for transceiver mechani-

cal attachment to the circuit board. They may also provide an optional con-

nection of the transceiver to the equipment chassis ground.

Photodetector Bias. This lead supplies bias for the PIN photodetector diode.

Receiver Signal Ground.

Receiver Signal Ground.

Received Recovered Clock Out. The rising edge occurs at the rising edge of

the received data output. The falling edge occurs in the middle of the received

data bit period.

Received Recovered Clock Out. The falling edge occurs at the rising edge

of the received data output. The rising edge occurs in the middle of the

received data bit period.

Receiver Signal Ground.

Receiver Power Supply.

Signal Detect.

Normal operation: logic one output.

Fault condition: logic zero output.

Received DATA Out. No internal terminations will be provided.

Received DATA Out. No internal terminations will be provided.

Logic

Family

NA

NA

NA

NA

PECL

PECL

NA

NA

LVTTL

PECL

PECL

2

Agere Systems Inc.

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