28F002BC 查看數據表（PDF） - Intel
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28F002BC Datasheet PDF : 37 Pages
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28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Start
Write 40H and
Byte Address
Write Data and
Data Address
Read
Status Register
No
SR.7 = 1
?
Yes
Full Status
Check if Desired
Program Complete
Bus
Operation
W rite
W rite
Read
Command
Comments
Program Data = 40H
Setup Addr = Byte to Program
Program Data = Data to Program
Addr = Location to Program
Status Register Data
Toggle CE# or OE# to Update SRD.
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent writes.
SR Full Status Check can be done after each write, or after
a sequence of writes.
Write FFH after the last write operation to reset device to
read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
0
1
SR.4 =
0
Program Successful
VPP Range Error
Program Error
Bus
Operation
Standby
Command
Comments
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4
1 = Program Error
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.4 is only cleared by the Clear Status Register command, in cases
where multiple bytes are programmed before full status is checked.
If error is detected, clear the status register before attempting retry
or other error recovery.
0578_06
Figure 7. Automated Programming Flowchart
20
PRELIMINARY
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