28F016XD-85 查看數據表（PDF） - Intel

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28F016XD-85

16-MBIT (1 MBIT x 16) DRAM-INTERFACE FLASH MEMORY

Intel 

28F016XD FLASH MEMORY

E

4.2 28F008SA—Compatible Mode Command Bus Definitions

Command

Notes

First Bus Cycle

Oper Addr Data(4)

Second Bus Cycle

Oper Addr Data(4)

Read Array

Write

X

xxFFH Read

AA

AD

Intelligent Identifier

1

Write

X

xx90H Read

IA

ID

Read Compatible Status Register

2

Write

X

xx70H Read

X

CSRD

Clear Status Register

3

Write

X

xx50H

Word Program

Write

X

xx40H Write

PA

PD

Alternate Word Program

Write

X

xx10H Write

PA

PD

Block Erase/Confirm

Write

X

xx20H Write

BA xxD0H

Erase Suspend/Resume

Write

X

xxB0H Write

X

xxD0H

ADDRESS

AA = Array Address

BA = Block Address

IA = Identifier Address

PA = Program Address

X = Don’t Care

DATA

AD = Array Data

CSRD = CSR Data

ID = Identifier Data

PD = Program Data

NOTES:

1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register

definitions.

4. The upper byte of the data bus (D8–15) during command writes is a “Don’t Care.”

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