ML2712CH 查看數據表（PDF） - Micro Linear Corporation
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ML2712CH Datasheet PDF : 22 Pages
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PRELIMINARY
CONTROL INTERFACES (CONTINUED)
ML2712
Data
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
Control Word A
VC1 VC2 PLL1 PLL2 CP1 CP2 PP1 PP2 LD1 LD2 PPW PB
x
Power Up Default
1
1
1
1
1
1
1
1
1
1
1
1
x
Control Word B
TX RX LBC DAC DCE COM CI1 CI2 CI3 CI4 CAL WB x
Power Up Default
0
0
0
1
0
1
1
1
1
1
1
1
x
Control Word C
MSB 1LO ND1 Counter LSB
MSB 1LO NS1 Swallow Counter LSB
x
Power Up Default
1
1
0
1
1
0
0
1
0
1
0
0
x
Control Word D
MSB 2LO ND2 Counter
2LO NS2 Counter
Reference Div.
x
MSB
LSB
Power Up Default
1
0
0
0
0
1
1
0
0
0
0
1
x
Control Word E
x
x
x
x MSB
8-bit DAC Voltage
LSB x
Power Up Default
x
x
x
x
0
0
0
0
0
0
0
0
x
0
0
1
0
1
0
Address
0
1
1
Address
1
0
0
Address
1
0
1
Table 4. Control Word Settings on the Serial Control Bus
Control Bit in CONTROL WORD A
ML2712 Circuits Enabled
VC1 VC2
PLL1 PLL2
CP1
CP2
1LO VCO 2LO VCO 1LO PLL
2LO PLL
1LO Charge 2LO Charge
Pump
Pump
0
0
0
0
0
0
ALL OFF
1
x
x
x
x
x
ON
x
x
x
x
x
x
1
x
x
x
x
x
ON
x
x
x
x
x
x
1
x
x
x
x
x
ON
x
x
x
x
x
x
1
x
x
x
x
x
ON
x
x
x
x
x
x
1
x
x
x
x
x
ON
x
x
x
x
x
x
1
x
x
x
x
x
ON
1
1
1
1
1
1
ALL ON (DEFAULT POWER UP CONDITION)
Table 5. VCO, PLL and Charge Pump Power Control Modes
CONTROL WORD A
Control Word A enables the VCOs, PLL dividers, PLL
charge pumps and voltage reference circuits;
programs the polarity of PLL charge pumps; and
programs the function of the Lock Detect (LD)
output.
Control Bits VC1, VC2, PLL1, PLL2, CP1, CP2
Two frequency synthesizers, 1LO and 2LO, each
contain a VCO and a PLL. This dual conversion
superheterodyne receiver uses the two local
oscillators to down convert the 2450 MHz ISM Band RF
signal. (Table 5).
All these circuit components are enabled individually
using CONTROL WORD A as defined in Table 4. For
the PLLs to operate, all control bits must be set to 1.
14
PRELIMINARY DATASHEET January, 2000
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