CA16A2CNN 查看數據表（PDF） - Agere -> LSI Corporation

零件编号

产品描述 (功能)

生产厂家

CA16A2CNN

CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

Advance Data Sheet

March 2001

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Timing Characteristics (continued)

Input Timing Mode 1

In the configuration shown in Figure 5, PHERR to

PHINIT has a zero delay (shorted on the PCB) and the

PCLK is used to clock 16-bit-wide data out of the cus-

tomer ASIC. The FIFO in the multiplexer ia 16-bits wide

and six registers deep.

The PCLK and PICLK signals respectively control the

READ and WRITE counters for the FIFO. The data

bank from the FIFO has to be read by the internally

generated clock (PCLK) only once after it has been writ-

ten by the PICLK input.

Since the delay in the customer ASIC is unknown, the

two clocks (PCLK and PICLK) might drift in respect to

each other and try to perform the read and writer oper-

ation on the same bank in the FIFO at the same time.

However, before such a clock mismatch can occur,

PHERR goes high and, if externally connected to

PHINIT, will initialize the FIFO provided PHINIT

remains high for at least two byte clocks. One to three

16-bit words of data will be lost during the initialization

of the FIFO.

OSCILLATOR

155.52 MHz ± 20 ppm

CLOCK

DATA

PCLK

TXREFCLK

DIVIDER

PLL

PICLK

INTERNAL

PCLK

16

TXD[0:15]

TIMING

GENERATOR

FIFO

D

Q

CUSTOMER LOGIC

PHERR

PHINIT

CENTERS

FIFO

LOCKDET

CA16 TRANSPONDER

1-1121(F).b

Figure 5. Block Diagram Timing Mode 1

Agere Systems Inc.

19

Share Link: