TA16S1FAA 查看數據表（PDF） - Agere -> LSI Corporation

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TA16S1FAA

TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

Data Sheet

March 2001

TA16-Type 2.5 Gbits/s Transponder with

16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Timing Characteristics (continued)

PCLK-to-PICLK Timing

After powerup or RESET, the LOCKDET signal will go

active, signifying that the PLL has locked to the clock

provided on the TXREFCLK input. The FIFO is initialized

on the third PICLK after LOCKDET goes active. The

PCLK-to-PICLK delay (tD) can have any value before

the FIFO is initialized. The tD is fixed at the third PICLK

after LOCKDET goes active. Once the FIFO is initial-

ized, PCLK and PICLK cannot drift more than 5.2 ns;

tCH cannot be more than 5.2 ns.

PCLK

tD

tD

PICLK

1ST

2ND

3RD

tCH

tCH

LOCKDET

ACTIVE

PCLK-TO-PICLK DELAY IS FIXED AND FIFO

IS INITALIZED AT THE THIRD RISING EDGE OF

PICLK AFTER LOCKDET GOES ACTIVE.

Figure 7. PCLK-to-PICLK Timing

1123(F)

Agere Systems Inc.

21

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