HFA3524 查看數據表（PDF） - Intersil

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HFA3524

2.5GHz/600MHz Dual Frequency Synthesizer

Intersil 

HFA3524

of equal value to R2 will need to be switched in parallel with

R2 during the initial lock period. We must also insure that the

magnitude of the open loop gain, H(s)G(s) is equal to zero at

wp’ = 2wp. KVCO, Kφ, N, or the net product of these terms can

be changed by a factor of 4, to counteract the w2 term present

in the denominator of Equation 3. The Kφ term was chosen to

complete the transformation because it can readily be

switched between 1X and 4X values. This is accomplished by

increasing the charge pump output current from 1mA in the

standard mode to 4mA in Fastlock.

Fastlock Circuit Implementation

A diagram of the Fastlock scheme as implemented in Intersil

Corporations HFA3524 PLL is shown in Figure 25. When a

new frequency is loaded, and the RF IcpO bit is set high, the

charge pump circuit receives an input to deliver 4 times the

normal current per unit phase error while an open drain

NMOS on chip device switches in a second R2 resistor

element to ground. The user calculates the loop filter

component values for the normal steady state

considerations. The device configuration ensures that as

long as a second identical damping resistor is wired in

appropriately, the loop will lock faster without any additional

stability considerations to account for. Once locked on the

correct frequency, the user can return the PLL to standard

low noise operation by sending an instruction with the RF

IcpO bit set low. This transition does not affect the charge on

the loop filter capacitors and is enacted synchronous with

the charge pump output. This creates a nearly seamless

change between Fastlock and standard mode.

GAIN

|<G(s) H(s)|

0dB

PHASE

G(s) H(s)

ωP

ωP’ = 2ωP

-90

φP

φP’

FREQUENCY

-180

FIGURE 24. OPEN LOOP RESPONSE BODE PLOT

CRYSTAL

REFERENCE

DIVIDER MAIN

1/N

1/R

REFERENCE

DIVIDER

PHASE

DETECTOR

fP

φR

fR Φ φP

FASTLOCK

fIN

CHARGE

PUMP

VP

DO

1X 4X

FOLD

LOOP FILTER VCO

C1

C2

R2’

R2

RFOUT

FIGURE 25. FASTLOCK CIRCUIT IMPLEMENTATION

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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