5962R9582401QQC 查看數據表（PDF） - Intersil

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5962R9582401QQC

Radiation Hardened 8-Bit CMOS Microprocessor

Intersil 

HS-80C85RH

Basic System Timing

The HS-80C85RH has a multiplexed Data Bus. ALE is used

as a strobe to sample the lower 8-bits of address on the Data

Bus. Figure 15 shows an instruction fetch, memory read and

I/O write cycle (as would occur during processing of the OUT

instruction). Note that during the I/O write and read cycle that

the I/O port address is copied on both the upper and lower

half of the address.

There are seven possible types of machine cycles. Which of

these seven takes place is defined by the status of the three

status lines (lO/M, S1, S0) and the three control signals (RD,

WR, and INTA). (See Table 10.) The status lines can be

used as advanced controls (for device selection, for

example), since they become active at the T1 state, at the

outset of each machine cycle. Control lines RD and WR are

used as command lines since they become active when the

transfer of data is to take place.

TABLE 5. HS-80C85RH MACHINE CYCLE CHART

STATUS CONTROL

MACHINE CYCLE

IO/M S1 S0 RD WR INTA

Opcode Fetch (OF)

0 11 0 1 1

Memory Read (MR)

0 10 0 1 1

Memory Write (MW)

0 01 1 0 1

I/O Read

(IOR)

1 10 0 1 1

I/O Write

(IOW)

1 01 1 0 1

Acknowledge (INA)

of INTR

1 11 1 1 0

Bus Idle

(BI) DAD Ack. of 0 1 0 1 1 1

RST, TRAP 1 1 1 1 1 1

HALT

TS 0 0 TS TS 1

A machine cycle normally consists of three T states, with the

exception of OPCODE FETCH, which normally has either

four or six T states (unless WAIT or HOLD states are forced

by the receipt of READY or HOLD inputs). Any T state must

be one of ten possible states, shown in Table 11.

TABLE 6. HS-80C85RH MACHINE STATE CHART

MACHINE

STATUS AND BUSES

CONTROL

STATE S1, S0 IO/M A8-15 AD0-7 RD, WR INTA ALE

T1

X

X

X

X

1

1 1†

T2

X

X

X

X

X

X0

TWAIT

X

X

X

X

X

X0

T3

X

X

X

X

X

X0

T4

1 0†† X

TS

1

10

T5

1 0†† X

TS

1

10

T6

1 0†† X

TS

1

10

TRESET

X TS TS

TS

TS

10

THALT

0 TS TS TS

TS

10

THOLD

X TS TS TS

TS

10

0 = Logic “0”

1 = Logic “1”

TS = High Impedance

X = Unspecified

† ALE not generated during 2nd and 3rd machine cycles of DAD

instruction.

†† IO/M = 1 during T4, T6 of INA machine cycle.

CLK

M1

M2

M3

T1

T2

T3

T4

T1

T2

T3

T1

T2

T3

T

A8-A15

AD0-7

ALE

PCH (HIGH ORDER ADDRESS)

(PC + 1)H

IO PORT

PCL

(LOW ORDER DATA FROM

ADDRESS) MEMORY

(INSTRUCTION)

(PC+1)L

DATA TO

MEMORY OR

PERIPHERAL

IO PORT

DATA FROM

MEMORY (I/O

PORT ADDRESS)

RD

WR

IO/M

STATUS

S1-S0 (FETCH)

10 (READ)

01 WRITE

11

FIGURE 15. 80C85RH BASIC SYSTEM TIMING

15

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