73K324BL-IH/F 查看數據表（PDF） - Teridian Semiconductor Corporation

零件编号

产品描述 (功能)

生产厂家

73K324BL-IH/F

CCITT V.22bis,V.23,V.22,V.21,Bell 212A Single-Chip Modem w/ Integrated Hybrid

Teridian Semiconductor Corporation 

73K324BL

CCITT V.22bis,V.23,V.22,V.21, Bell 212A

Single-Chip Modem w/ Integrated Hybrid

DATA SHEET

TONE REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

TR

RXD TRANSMIT TRANSMIT TRANSMIT

011 OUTPUT GUARD ANSWER

DTMF

CONTROL TONE

TONE

DTMF

3

BIT

NAME

CONDITION DESCRIPTION

DTMF 2/

4-WIRE

FDX

DTMF 1/

EXTENDED

OVER-

SPEED

DTMF 0/

G.T./ANSW./

CALLING//

SCT

TONE/SEL

D6 D5 D4 D0 D0 interacts with bits D6, D5, and D4 as shown

D0, D4,

D5, D6

DTMF 0/

Guard Tone/

X X 1 X Transmit DTMF tones (overrides all other functions).

Must be in V.22 mode during DTMF transmission

Answer Tone/

Calling/SCT

1 0 0 0 Select 1800 HZ guard tone if in V.22bis or V.22 and

Answer mode in CR0.

Tone/

Transmit

1 0 0 1 Select 550 Hz guard tone if in V.22bis or V.22 and

Answer mode in CR0.

Select

Note: Bit D0 also selects the answer tone detected in Originate mode, see

Detect Register Special Tone Detect (bit D2) for details.

1 0 0 0 1300 Hz calling tone will be transmitted if V.22, V.22bis

or V.23 Originate mode is selected in CR0.

X 1 0 0 Transmit 2225 Hz Answer Tone. Must be in DPSK

Answer mode..

X 1 0 1 Transmit 2100 Hz Answer Tone. Must be in DPSK

Answer mode.

1 0 0 1 900 Hz SCT (soft carrier turnoff) tone transmitted in V.23

75 bps Receive mode. (CR0 bit D0 = 1)

D4 D1

D1 interacts with D4 as shown.

D1

DTMF 1/

00

Asynchronous QAM or DPSK +1% -2.5%. (normal)

Extended

Overspeed

01

Asynchronous QAM or DPSK +2.3% -2.5%. (extended

overspeed)

D4 D2

D2

DTMF 2/

00

Selects 2-wire duplex or half duplex

4 Wire FDX

01

D2 selects 4-wire full duplex in the modulation mode

selected. The receive path corresponds receive mode

selected by the ANS/ORIG bit CR0 D0 in terms of high or

low band operation. The transmitter is in the same band

as the receiver, but does not have magnitude filtering or

equalization on its signal as in the receive path.

Page: 15 of 34

© 2005, 2008 TERIDIAN Semiconductor Corporation

Rev 6.1

Share Link: