73K324BL-IHR 查看數據表（PDF） - Teridian Semiconductor Corporation

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73K324BL-IHR

CCITT V.22bis,V.23,V.22,V.21,Bell 212A Single-Chip Modem w/ Integrated Hybrid

Teridian Semiconductor Corporation 

73K324BL

CCITT V.22bis,V.23,V.22,V.21, Bell 212A

Single-Chip Modem w/ Integrated Hybrid

DATA SHEET

SPECIAL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

SR

0

TXBAUD RXUN-

0

TXD

SIGNAL

SIGNAL

0

101

CLOCK

DSCR

SOURCE QUALITY QUALITY

DATA

LEVEL

LEVEL

SELECT 1 SELECT 0

BIT

NAME

DESCRIPTION

D7, D4, D0

Not used at this time. Only write zeros to these bits.

D6

TXBAUD CLK TXBAUD clock is the transmit baud-synchronous clock that can be used to

synchronize the input of arbitrary quad/di-bit patterns. The rising edge of

TXBAUD signals the latching of a baud-worth of data internally. Synchronous

data to be entered via the TXDALT bit, CR3 bit D7, should have data

transitions that start 1/2 bit period delayed from the TXBAUD clock edges.

D5

RXUNDSCR This bit outputs the data received before going to the descrambler.

Data

This is useful for sending special unscrambled patterns that can be used for -

signaling.

D3

TXD Source This bit selects the transmit data source; either the TXD pin if zero or the

TXDALT if this bit is a one. The transmit pattern bits D7 and D6 in CR1

override either of these sources.

D2, D1

Signal Quality

Level Select

The signal quality indicator is a logical zero when the signal received is

acceptable for low error rate reception. It is determined by the value of the

mean squared error (MSE) calculated in the decision process when

compared to a given threshold. This threshold can be set to four levels of

error rate. The SQI bit will be low for good or average connections. As the

error rate crosses the threshold setting, the SQI bit will toggle at a 1.66 ms

rate. Toggling will continue until the error rate indicates that the data pump

has lost convergence and a retrain is required. At that point the SQI bit will be

a one constantly. The SQI bit and threshold selection are valid for QAM and

DPSK only and indicates typical error rate.

D2 D1 THRESHOLD VALUE

UNITS

0

0

10-5

BER (default)

0

1

10-6

BER

1

0

10-4

BER

1

1

10-3

BER

NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a one and addressing CR3. This

register provides functions to the 73K324BL user that are not necessary in normal communications. Bits

D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6 must be

returned to a zero.

Page: 19 of 34

© 2005, 2008 TERIDIAN Semiconductor Corporation

Rev 6.1

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