73M1903-IVTR 查看數據表（PDF） - Teridian Semiconductor Corporation

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73M1903-IVTR

Modem Analog Front End

Teridian Semiconductor Corporation 

73M1903 Data Sheet

DS_1903_032

2.2.3 Control Register (CTRL 13): Address 0Dh

Reset State 48h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Xtal1

Xtal0

Reserved Reserved Unused Nrst2

Bit 1

Nrst1

Bit 0

Nrst0

Xtal[1:0] :

00 = Xtal osc. bias current at 120 μA

01 = Xtal osc. bias current at 180 μA

10 = Xtal osc. bias current at 270 μA

11 = Xtal osc. bias current at 450 μA

If OSCIN is used as a Clock input, “00” setting should be used to save power(=167 μA at 27.648 MHz).

Nrst[3:0] represents the rate at which the NCO sequence register is reset.

The address 0Dh must be the last register to be written to when effecting a change in PLL.

2.2.4 Control Register (CTRL 14): Address 0Eh

Reset State 00h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Frcvco PwdnPLL Reserved Unused Unused Unused

Bit 1

Unused

Bit 0

Unused

Frcvco = 1 forces VCO as system clock. This is reset upon RST, PwdnPLL = 1 or ENFE = 0. Both

PwdnPLL and ENFE are delayed coming out of digital section to keep PLL alive long enough to transition

the system clock to crystal clock when Frcvco is reset by PwdnPLL or ENFE.

PwdnPll = 1 forces Power down of PLL analog section.

12

Rev. 2.0

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